`timescale 1ns/1ps
module DDS_model_tb;

	reg				clk						; 
	reg				rst_n						;
	reg				key						;
	reg  [1:0]		model_selA,model_selB;
	reg  [31:0]		FwordA,FwordB			;
	reg  [11:0]		PwordA,PwordB			;
	wire [13:0]		dataA,dataB				;

	DDS_model DDS_modelA(			// 通道A输出
		.clk			(clk			), 
		.rst_n		(rst_n		),
		.key			(key			),
		.model_sel	(model_selA	),
		.Fword		(FwordA		),
		.Pword		(PwordA		),
		.data			(dataA		)
	);

	DDS_model DDS_modelB(			// 通道B输出
		.clk			(clk			), 
		.rst_n		(rst_n		),
		.key			(key			),
		.model_sel	(model_selB	),
		.Fword		(FwordB		),
		.Pword		(PwordB		),
		.data			(dataB		)
	);
	
	initial clk = 1;
	always #10 clk = ~clk;
	
	initial begin
		rst_n = 0;
		key = 0;
		// 0度正弦波
		model_selA = 2'b00;
		FwordA = 65536;
		PwordA = 0;
		// 90度正弦波
		model_selB = 2'b00;
		FwordB = 65536;
		PwordB = 1024;
		#201;
		rst_n = 1;
		#5000000;
		// 
		FwordA = 65536*1024;
		PwordA = 0;
		
		FwordB = 65536*1024;
		PwordB = 2048;
		#1000000;
		$stop;
	end


endmodule 